Phase-locked loops (PLLs) and delay-locked loops (DLLs) may be employed in processor and memory integrated circuits to cancel on-chip clock amplification and buffering delays and to improve input/output (I/O) timing margins. DLLs may offer an alternative to PLLs due to their better jitter performance, inherent stability and simpler design. DLLs may lock to a specific frequency and have a known delay through a voltage control delay line (VCDL). One implementation of a DLL may be to have an input signal (i.e., a clock phase 0 signal) received by a VCDL that outputs a clock phase 180 signal. A DLL may attempt to “lock” the clock phase 0 signal and the clock phase 180 signal by comparing edges of each of these signals.